Integrated circuits transmit and receive electrical signals to and from other circuitry using input and output “cells” designed for that purpose. The physical connection between each input or output cell and outside circuitry is conventionally made by bonding a small wire to a bonding “pad”, i.e., an extended and exposed conductive region located on one of the circuit's metal layers. For an input cell, receiving circuitry connects to the bonding pad. For an output cell, a transmitter or driver circuit connects to the bonding pad. Typically, both input and output cells also contain Electro-Static Discharge (ESD) protection circuitry that attempts to clamp large transient voltages (inadvertently applied to a bonding pad) before those voltages can damage a receiver or driver.
FIGS. 1, 2, and 3 illustrate three aspects of a simple output cell 20. Referring first to FIG. 1, P-channel MOS (PMOS) transistor 22 and N-channel (NMOS) transistor 24 operate as a complementary field-effect transistor (FET) pair signal driver. When signal IN is at a high voltage, transistor 22 is turned off and transistor 24 is turned on, pulling output pad 25 down towards Vss. Conversely, when signal IN is at a low voltage, transistor 24 is turned off and transistor 22 is turned on, pulling output pad 25 up towards Vdd.
PMOS transistor 26 and NMOS transistor 28 provide ESD protection for cell 20. Note that the gate of transistor 26 is permanently connected to Vdd, and the gate of transistor 28 is permanently connected to Vss, ensuring that these transistors are permanently off. But as shown in FIG. 2, transistors 26 and 28 contain diode structures that provide protection against voltage spikes. PMOS transistor 26 protects the cell from pad voltages much greater than Vdd, and NMOS transistor 28 protects the cell from pad voltages much less than Vss.
FIG. 3 shows a cross-section of transistors 26 and 28. Within PMOS transistor 26, a diode junction exists between the P+ drain diffusion 36 (connected to output pad 25) and the N-well drain diffusion 32 (connected to Vdd). Thus when the voltage at output pad 25 is slightly higher than Vdd, this diode junction is forward biased and current can flow from the pad to the Vdd voltage rail, clamping the pad voltage to a safe level.
Similarly, within NMOS transistor 28, a diode junction exists between the N+ drain diffusion 40 (connected to output pad 25) and the P-substrate 30 (connected to Vss). Thus when the voltage at output pad 25 is slightly lower than Vss, this diode junction is forward biased and current can flow from the Vss voltage rail to the pad, again clamping the pad voltage to a safe level.